This invention relates to arbitration of access to a system bus, and more particularly, to arbitration between devices having different levels of access priority to the system bus.
In many personal computers (PCs), a motherboard is provided with an implementing integrated circuit ("chip") set. The devices or components of the implementing chip set are coupled to one another through a system bus. The motherboard is usually provided with a number of extension connectors so other devices or interfaces/bridges may be coupled to the system bus. For example, the peripheral component interconnect (PCI) bus is frequently used in PCs to couple an implementing chip set for a PC to the devices and interfaces/bridges which may be coupled to the expansion connectors. Devices, which may be coupled in an extension connector, include Ethernet interfaces, SCSI interfaces, Host/PCI bridges, PCI/Legacy bridges, video, sound, and E-IDE printed circuit cards.
A typical system using a PCI bus has two or three card connectors and two or three PCI loads on the motherboard. However, a PCI bus is limited to a maximum of ten electrical loads. For printed circuit cards coupled to a connector, the connector represents one load and the card represents a second load. As a result, the maximum load for a PCI bus may be reached before a user has coupled all of the components desired for a system. Another restriction which limits the number of devices which may be coupled to a system bus is the arbitration scheme used to control access to the system bus. For example, in some PCI bus systems, the number of bus masters used to control device access to the system bus is limited to four because that is the maximum number of request/grant (REQ#/GNT#) pairs that can be handled by the central bus arbiter.
In an effort to overcome the limitations of a system bus such as the maximum number of electrical loads and maximum number of bus masters, multi-function devices which couple more than one function to a single system bus have been developed. These devices represent the same number of electrical loads as a single function device; however, they provide more functions. Additionally, the multi-function device only requires one request/grant pair for all functions and thus, appears as a single bus master to the central arbiter of the system bus. In this type of system, the bus master arbitrates access for the request/grant pair between the functions.
In a PCI system, the central arbiter receives request signals from PCI devices or bus masters and determines which device or bus master receives a grant signal. In response to receipt of a grant signal, a PCI device sends or receives data over the system bus. Where a multiple function device is coupled to a PCI bus through a bus master, the bus master must arbitrate between the multiple functions which the bus master couples to the system bus. In previously known systems, contentions between multiple functions coupled to a single bus master are resolved by prioritizing the functions for system bus access. In this scheme, each function is assigned a numerical priority level, usually from 0-7, with zero being the lowest priority and 7 being the highest priority.
While the prioritizing of the system bus access requests from the various functions of a multi-function PCI device enables a bus master to resolve competing requests for system bus access, prioritization of the requests presents other issues. For example, a high priority function may dominate access to the system bus to the extent of completely or substantially excluding a lower priority function from bus access. In an effort to address this limitation, rotating prioritizing schemes have been developed. Typically, these arbitration schemes statistically evaluate the proportionate amount of time a device is being given access to the system bus and reduce the likelihood of one function blocking the other functions by changing the system access function priorities. The modification of the function priorities is typically performed on a periodic basis. As the priority for a function is increased, it is able to gain more access to the system bus and, consequently, receive and transmit data over the bus without contending with the same higher priority access requests.
While the rotating priority level addresses some aspects of the problem caused by static priority assignment, it still causes other system access problems. For example, system transmissions and receptions over a PCI bus are performed in burst mode. To complete a transmission or a reception, several bursts may be required. Thus, a device may be at the highest level of priority for system bus access for a portion of a transmission or reception and at a lower priority level for the remainder of the transmission or reception. Consequently, it may be some time before the device is able to acquire bus access from the higher priority functions to complete the transmission or reception.
What is needed is a system and method for system bus arbitration between multiple functions so that data transfers may be more timely completed.